The present invention relates to fabricating a semiconductor device and, more particularly, to a transistor in a semiconductor device and a method for fabricating the same.
Recently, as semiconductor devices become more highly integrated, a conventional two-dimensional transistor structure exhibits various limitations. That is, the conventional two-dimensional transistor structure cannot obtain a data retention characteristic in a highly integrated memory device and cannot satisfy a current drivability required for a high speed device.
In order to overcome such limitations, transistors having various structures have been suggested.
FIG. 1 illustrates a perspective view of a conventional fin field effect transistor (fin FET) (hereinafter, referred to as a fin transistor). The fin transistor is provided to obtain the current drivability for a high speed device.
As shown in FIG. 1, the fin transistor includes a substrate 11. A part of the substrate 11 where a channel will be subsequently formed protrudes in a direction perpendicular to an isolation layer 12 to form a fin active area 11A. A gate electrode 13 crossing the fin active area 11A is formed on the isolation layer 12. Since three surfaces of the substrate 11 surrounded by the gate electrode 13 are used as a channel of the transistor, the current drivability of the device may be improved. Reference symbols S and D represent a source region and a drain region, respectively.
However, because the channel of the fin transistor is defined by three surfaces, it is difficult to raise a threshold voltage above a certain level. Accordingly, the fin transistor is rarely used as a cell transistor in a memory device such as a dynamic random access memory (DRAM) which requires a high threshold voltage of approximately 0.8 V or more. The reason for this is that when the threshold voltage is not raised above a certain level in the memory device such as the DRAM, an off-leakage characteristic is considerably deteriorated. Therefore, in order to employ the fin transistor as a cell transistor in the memory device, increasing the threshold voltage of the fin transistor is required.
Generally, an NMOS transistor is employed as a cell transistor in the memory device. Accordingly, a method to increase the threshold voltage of the fin transistor uses a polysilicon layer doped with p-type impurities (for instance, boron B) (hereinafter, referred to as P+ polysilicon layer) as a gate electrode of a fin transistor instead of using a conventional polysilicon layer doped with n-type impurities (for instance, phosphorus P) (hereinafter, referred to as N+ polysilicon layer). Theoretically, a work function of the P+ polysilicon is greater than that of the N+ polysilicon by approximately 1.0 eV so that the threshold voltage of the fin transistor can be increased by approximately 0.8 V to approximately 1.0 V due to the replacement of the gate electrode mentioned above.
FIG. 2A illustrates a cross-sectional view of a conventional NMOS transistor structure using a P+ polysilicon gate electrode, and FIG. 2B illustrates an energy band diagram for explaining a limitation of the transistor structure shown in FIG. 2A. The transistor in FIG. 2A has a recess gate structure to obtain a data retention characteristic in a highly integrated memory device.
As shown in FIG. 2A, the transistor includes a gate 24. A P+ polysilicon gate electrode 24A, a low resistance gate electrode 24B and a gate hard mask 24C are stacked on a recess 23 to form the gate 24. The recess 23 is formed by etching an active area of a substrate 21. The active area is defined by an isolation layer 22. A gate insulation layer 25 is interposed between the gate 24 and the substrate 21. Gate spacers 26 are formed on opposite sidewalls of the gate 24. N-type source/drain regions 27 are formed in the substrate 21 at both sides of the gate 24.
However, when the NMOS transistor having the P+ polysilicon gate electrode as shown in FIG. 2A is used, the following limitations may occur. The limitations will be described with reference to the energy band diagram of FIG. 2B by comparing a case where the P+ polysilicon gate electrode is formed on a gate oxide layer and an n-type source/drain junction with a case where an N+ polysilicon gate electrode is formed on the gate oxide layer and the n-type source/drain junction.
Generally, as described above, a work function of the P+ polysilicon φP is approximately 5.2 eV and the work function of the N+ polysilicon φN is approximately 4.2 eV so that the work function of the P+ polysilicon φP is greater than that of the N+ polysilicon φN by approximately 1.0 eV. Accordingly, referring to the energy band diagram of FIG. 2B, when using the P+ polysilicon gate electrode, it shows a greater band bending phenomenon (refer to 200 in FIG. 2B) at a gate oxide layer/junction interface as a difference in the work functions between the P+ polysilicon and the N+ polysilicon becomes greater. Therefore, when using the P+ polysilicon gate electrode, a gate induced drain leakage (GIDL) characteristic is degraded compared to the case when using the N+ polysilicon gate electrode. Accordingly, the data retention characteristic of the memory device is also degraded.
The degradation of the GIDL characteristic also occurs in the fin transistor structure shown in FIG. 1 even if the P+ polysilicon gate electrode is used instead of the N+ polysilicon gate electrode to improve the threshold voltage.
Accordingly, when fabricating the device employing the fin transistor or the recess gate transistor, raising a threshold voltage and improving the GIDL characteristic is required.